Do Something Wonderful!
Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.
Are you passionate about computer graphics and disrupting the industry with your innovation, and working with leading Engineers on Intel's latest GPU architecture. Do you love collaborating with diverse teams to help achieve best-In-class visual experiences that enable users to immerse themselves in a new visual future? Then the GPU Hardware IP team at Intel has opportunities for you. Our Hardware development team designs and validates the future processors that are the engines behind our GPUs. We are looking for a DFT Engineer to join our team who is ready to make significant impacts on the future of graphics and visual computing technology.
As a member of the Graphics Hardware DFT group you will be responsible for, but not limited to, working on the design, RTL/GLS validation, and automation in the following DFT domains: TAP Controller, Scan, Array DFT (PBIST/MBIST), IO DFT, PLL DFT or HVM Reset.
Behavioral skills we are looking for:
Strong written and verbal communication skills
Leadership ability in driving execution
Strong teamwork, problem solving and influencing skills
This is an entry level position and will be compensated accordingly.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research and relevant previous job and/or internship experience.
Minimum Qualifications:
Bachelors Degree in Electrical Engineering, Computer Engineering, or related STEM degree with 1+ years experience in the following:
ASIC design flow (logic design, integration, or verification)
Programming or scripting languages (such as Python or Perl)
Preferred Qualifications:
Masters Degree in Electrical Engineering, Computer Engineering, or related STEM degree.
Familiarity with at least one of the key DFT features such as TAP/JTAG, Scan/ATPG or Array DFT (MBIST/PBIST)
EDA tools such as ATPG tools, Siemens Tessent Shell, Synopsis VCS simulation and/or debug tools
Structural design flows, including timing, routing, placement or clocking analysis
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$91,500.00-$137,436.00Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.