Apply directly to jobs in best companies
Search Companies / Jobs
 
Post Silicon Debug Pathfinding Engineer at Intel
Santa Clara, United States


Job Descrption

Job Details:

Job Description: 

Intel's Post Silicon Debug technology pathfinding team is responsible for next generation ion beam technology, circuit edit, and transistor probe technology developments. The Circuit Edit Research and Development Engineer's responsibilities include:

  • Execution of experiments for new generations of focused ion beam (FIB) platforms and ion beam technologies (e.g., Xenon Plasma FIB; Gallium FIB; Neon/Helium FIB; Cold Beam)

  • Provide analytical support on ion beam machined samples, including SEM, cross-section analysis, TEM / EDS analysis, mechanical probing, device testing, and electrical characterization.

  • Providing silicon debug support on Intel's leading-edge server and client products.


Additional responsibilities include:

  • Collaborating with the operation support team to develop and improve new circuit editing processes for the current and next-generation node

  • Working with circuit designers, component debug, platform validation engineering on direct write device modification and node access strategies.

  • Working with process development engineers on developing best practices for ion beam machining for defect analysis.

  • Strong interest in hands on application development work.

  • Good communication skills, ability to create training and documentation,

  • Ability to work both independently and collaboratively with teams across multiple organization and geographies.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelor's degree in electrical engineering, computer engineering, chemical engineering, material sciences, physics or any STEM related degree with 4+ years of experience or

Master's degree in electrical engineering, computer engineering, chemical engineering, material sciences, physics or any STEM related degree with 3+ years of experience or

PhD in any STEM related field with 1+ years of experience
Experience in 5 or more the following:

  • Device physics and integrated circuit knowledge

  • Circuit design and layout

  • Semiconductor fabrication process

  • Silicon or package physical failure analysis

  • Circuit Edit applications development or related fields

  • Scanning Electron Microscopy, Transmission Electron Microscopy, Focused Ion Beam system operations

  • Vacuum technology

  • Device performance characterization, such as using parametric analyzer

  • General knowledge of electronics, Unix, PC Skills and Microsoft Office.


Preferred Qualifications:

  • Additional hands-on TEM, EDS, SIMS, pico-probe station, and light optical microscope experience are valuable.

  • Controlled design of experiments

  • Process change control.

  • Surface chemical analysis (EDX, Auger, SIMS, etc.),

  • Circuit debug / validation

  • Plasma etch/chemical vapor deposition desired.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, California, Santa Clara

Additional Locations:

US, California, Folsom, US, Oregon, Hillsboro

Business group:

Manufacturing and Product Engineering (MPE) is responsible for test development across product segments, supporting 95% of Intel's revenue. We deliver comprehensive pre-production test suites and component/physical debug capabilities to enable high quality, high volume manufacturing.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:  https://www.intel.com/content/www/us/en/jobs/benefits.html


Annual Salary Range for jobs which could be performed in

US, California:$105,797.00-$175,105.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will require an on-site presence.

Complete form below to directly Send your CV / Linkedin Profile to Post Silicon Debug Pathfinding Engineer at Intel.
@
You will receive all responses from employer on this email
Example: Application for the post of 'Accountant'
Example: Introduce your self and give purpose of your application
*All fields are mandatory.
INTEL
49 jobs found
IFS, Design For Test (DFT) Engineer at Intel
Hillsboro, United States
Product Development Engineer - Testchip Post-Si execution at Intel
Folsom, United States
SoC Logic Design Engineer at Intel
Folsom, United States
Facilities Mechanical Exhaust Engineer at Intel
Hillsboro, United States
Business Development Manager – Data Center AI Solutions Partner at Intel
Santa Clara, United States
Fab11XFab9 Administrative Assistant at Intel
Rio Rancho, United States
Post Silicon Debug Pathfinding Engineer at Intel
Santa Clara, United States
Facilities Technician - Ultra Pure Water / Industrial Waste at Intel
Rio Rancho, United States
DFT Engineer at Intel
Folsom, United States
1 2 3 4 5