Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience
  
• 4 years of experience in logic design, debug, and timing/power closure
  

Preferred qualifications:

• Master's in Electrical Engineering, Computer Science, or equivalent degree
• 8 years of experience in ASIC design
  
• 3 years of experience working on PCIe design
  
• Experience interacting with software, system hardware, and other cross-functional teams
  
• Experience defining SoC IP interfaces and methodologies. Experience designing SOC chassis and/or connectivities
  
• Experience developing common library RTL modules. Experience working on PCIe verification and bringup
  

About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

As a SoC Design Engineer, you will join a team working on SoC-level RTL design for our data center acclerators. You will design RTL IP with the focus on PCIe subsystem, also participate in developing infrastructure and methodology that form the foundation of our SoCs (i.e., clocking, reset, error handling, debug, chip management and SOC chassis etc.). You will build a global understanding of how our accelerators are built from concept to production. This is a highly cross-functional role that will require you to coordinate and co-design with our software and system hardware counterparts. In this role, you will utilize, a background in RTL design, domain knowledge of PCIe, and the anility to leadi multi-faceted efforts involving many stakeholders.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Contribute to the architecture and microarchitecture of global SoC functionality.
• Develop SystemVerilog RTL to implement logic for ASIC/SoC products according to established coding and quality guidelines.
• Contribute to chip-wide design methodology.
• Work closely with software and system hardware teams to co-design solutions.