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Product Engineer, Principal at d-Matrix

Santa Clara, United States

Job Descrption

d-Matrix has fundamentally changed the physics of memory-compute integration with our digital in-memory compute (DIMC) engine. The “holy grail” of AI compute has been to break through the memory wall to minimize data movements. We’ve achieved this with a first-of-its-kind DIMC engine. Having secured over $154M, $110M in our Series B offering, d-Matrix is poised to advance Large Language Models to scale Generative inference acceleration with our chiplets and In-Memory compute approach. We are on track to deliver our first commercial product in 2024. We are poised to meet the energy and performance demands of these Large Language Models. The company has 100+ employees across Silicon Valley, Sydney and Bengaluru.

Our pedigree comes from companies like Microsoft, Broadcom, Inphi, Intel, Texas Instruments, Lucent, MIPS and Wave Computing. Our past successes include building chips for all the cloud hyperscalers globally - Amazon, Facebook, Google, Microsoft, Alibaba, Tencent along with enterprise and mobile operators like China Mobile, Cisco, Nokia, Ciena, Reliance Jio, Verizon, AT&AT. We are recognized leaders in the mixed signal, DSP connectivity space, now applying our skills to next generation AI.

Location:

Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week..

What you will do:

Looking for an experienced semiconductor product engineer with back- ground in:

• Good understanding of ATE development.

• PVT characterization for data sheet

• Has extensive yield management experience in FinFet, wafer sort, work with internal teams on test margin issues or with the wafer fab on process related yield limiters. Understands how to map the bin distribution into how is yielding by the area of the chip to determine if the yield fall out is expected. Also extensive experience with final test yield improvement looking for pattern margin issues or parametric yield limiters

• Has extensive experience working on test pattern margin issues ensuring test pattern margin is not the cause of fall out

• Has extensive wafer fab experience, knows FinFet process.

• Has extensive experience in product characterization, defining the wafer splits, identifying units representing the process window to allow for meaningful characterization to be completed to define base line

• Can define voltage margining, and temp requirements for characterization.

• Has extensive experience in data mining looking for trends

• Has background in reliability, drives tests needed in ATE flow to remove week die or devices

• Extensive experience in yield management, proven track record of improving wafer sort and final test yield

• Device failure analysis experience, locating defects within the design working with design engineering to allow for physical failure analysis

• Hs experience building yield models

• Has experience defining binning strategies for die or package tested parts

What You Will Bring:

• BS In Electrical Engineering, MS preferred with 10+ Years of Industry Experience

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.

d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

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